A synergistic fault tolerance framework for Mbit 28nm embedded RRAM

Resistive Random Access Memory (RRAM) technologies represent a promising frontier in next-generation non-volatile memory devices. They combine an operating speed and endurance superior to Flash memories with cost-effectiveness that challenges DRAMs. This paper delves into the RRAM challenges, examining the fault distribution in advanced RRAM configurations and the interplay between existing error correction codes (ECCs) and design assist techniques like Write Verify Algorithms. Our investigation reveals the limitations of current approaches and underscores the necessity for a holistic system-level fault detection, analysis, and repair solution. Through a comprehensive case study, we introduce and evaluate a novel scheme aimed at co-optimizing these elements to enhance RRAM reliability. The contributions of this work not only address a critical gap in the current understanding and application of RRAM but also lay the groundwork for future research and development in memory technologies.