A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control

A dynamic element matching (DEM) decoder with integrated mismatch calibration control for high-speed current-steering digital-to-analog converters (CS-DACs) and CSDAC- based direct digital frequency synthesizers (DDFSs) is studied and presented. The DEM algorithm achieves very good averaging of mismatch-induced errors in the succeeding CS-DAC. It features a minimum element transition rate, therefore opimizing the power dissipation and ensuring minimal glitch energy at the output. Due to the chosen network-based architecture, with only a few modifications of the hardware, the decoder allows the integration of a comprehensive current source mismatch calibration that can be fully operated in the background and even in parallel to the regular DEM operation. A proof-ofconcept hardware implementation of the presented decoder was fabricated in a 22-nm FD-SOI CMOS process and characterized in a high-speed DDFS system with a sampling rate of 5 GHz. Measurements reveal a significant improvement in the spurious free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) when the calibration and DEM are enabled. Compared to the state-of-the-art (SoA), the presented DDFS achieves one of the best figures of merit.