Impact of Wave Pipelining on NoCs for Heterogeneous Monolithic 3D SoCs

Monolithic 3D (M3D) integration technology for 3D System-on-Chip (SoC) designs dramatically expands the optimization potential of 3D Network-on-Chips (NoCs). As technology nodes evolve, design limitations shift from computation to communication, directly impacting the link delay of NoCs. M3D integration further intensifies this impact due to fabrication-related degradation on interconnects. To overcome link delay limitations, wave pipelining is a suitable solution. It allows for increased frequency and improved link throughput. This paper analyzes the impact of using wave pipelining to improve link performance in 3D NoCs. Here, we focus on heterogeneous 3D NoC architectures, as different technology nodes across tiers and processing units with varying footprints result in NoC designs with non-uniform topologies. The “RatatoskrM3D” simulator is used to perform various simulations, and the results indicate an overall improvement in NoC performance for various 3D NoC topologies with different clock frequencies across layers.