Exploring the Design Space of 32x32 Approximate Reduced Complexity Wallace Multipliers

In the realm of nano-scale technology, integrated circuits are focused on enhancing speed while minimizing power consumption and physical footprint. This demand has given rise to the concept of approximate computing, which is particularly vital for error-tolerant applications such as multimedia, machine learning, signal processing, and scientific computing. This study delves into the characteristics of various approximate reduced complexity Wallace multipliers, evaluating their accuracy, area usage, power consumption and delay. Specifically, the research centers on approximating calculations during the partial product reduction phase by substituting conventional full adders with approximate ones. The findings highlight the variability in introduced error, area and power requirements based on the combination and placement of these approximate adders within the partial product reduction stage. Using a Genetic Algorithm, we successfully reduce the size of our approximate multiplier by 61% of the exact multiplier's size, and we also observe a power reduction by 65% of the exact multiplier's power consumption. The proposed methodology offers insights for designers in selecting the most suitable configuration of approximate adders for the partial product reduction stage in a reduced complexity Wallace multiplier, tailored to the specific demands of their application.