Efficient FPGA Architecture for Transient State Estimation in Smart Grid Applications

In the realm of power systems engineering, heightened attention has been directed towards the concept of Transient State Estimation (TSE) due to its potential for enhancing system analysis within smart grids. This paper presents an efficient approach to address challenges in power grid monitoring by introducing adaptive architectures for real-time power system estimation, focusing on the pivotal role of TSE in enhancing grid resilience and efficiency. Leveraging the Vitis High-level Synthesis (HLS) tool and the Xilinx Zynq UltraScale+ MPSoC ZCU104 platform, the study proposes four distinct FPGA architectures. These architectures are systematically optimized for latency and resource utilization, emphasizing the delicate balance between these factors. The achieved goal through the paper is to demonstrate the feasibility of supporting real-time TSE for a representative network via an FPGA implementation.