Modeling and Analysis of Parasitic Elements Influence on Dynamic Characteristics of Microelectronic Systems

The paper examines the degree of influence of parasitic layout elements on the key dynamic characteristics of microelectronic systems. Using a 14-bit digital to analog converter with a conversion frequency of 1 GHz as an example, we analyzed the influence of parasitic capacitances and resistances on such converters’ dynamic characteristics. We made a theoretical estimate of MOS transistor intrinsic parasitic capacitances using most common technology parameters for 180 nm CMOS. We showed that layout parasitic capacitances and resistances jointly increase the settling time of the digital to analog converter signal from 0.8 ns to 2.5 ns and thus reduce the conversion frequency by more than three times to 400 MHz. We concluded that the procedure for reducing the influence of layout parasitic elements is mandatory when designing precision integrated circuits such as high-bit digital to analog and analog to digital converters. Without using special techniques to counteract layout parasitic elements, it is not possible to develop a high-frequency digital to analog converter with a resolution of 14 bits or higher.