The 5th Order Single-Bit Sigma-Delta Modulator with Passive Adder Design

This paper deals with design and performance analysis of single bit 5th order sigma-delta modulator in 180 nm CMOS. The key issue of the proposed design is relatively high SNR and SFDR within operating bandwidth. The modulator is clocked with 12.8 MHz at 1.8 V power supply to achieve noise floor of $\gt \mathbf{1 2 0} \mathbf{~ d B}$ across $\mathbf{1 0 0} \mathbf{~ k H z}$ bandwidth. Noise transfer function synthesis, filter architecture development and transistor-level design have been considered. Chain of integrators with weighted feed-forward summation has been chosen for loop filter implementation to maintain low nonharmonic distortions and improve linearity of the modulator. Single bit quantizer with passive adder have promoted to avoid extra capacitors at a summation node. Switched capacitor approach has been applied for minimization of clock jitter impact on total noise and for a process tolerance of the loop filter coefficients. Simulation results (including post-layout simulations) have demonstrated highlighted performances. The switched capacitor $\mathrm{kT} / \mathrm{C}$ noise has limited noise floor near 120 dB across the band of interest. While a quantization, noise has been as low as 150 dB.