A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

This article introduces a novel low-dropout (LDO) regulator based on a flipped-voltage follower (FVF) design, achieving a rapid 4 ns settling time. Tailored for high bandwidth memory generation 3 (HBM3) applications, it minimizes power supply-induced jitter (PSIJ), crucial in high-performance computing (HPC). The design integrates advanced bandwidth extension techniques, including active inductors and self-adaptive bias strategy. Additionally, a two-step digital approach significantly enhances performance over analog solutions. The prototype, occupying only 0.0061 mm2, achieves 40 mV undershoot and 46 mV overshoot voltage with 20 pF load capacitance, significantly enhancing the eye width of the write data strobe (DQS) clock in HBM3 to 424 mUI from 303 mUI, demonstrating its efficacy in HPC environments.