Study of Storage Capacity of Charge Trap EAROM NAND Memory Designed for Integration with VeSTIC Technology

This paper presents a study of increased information storage capabilities of single memory cell of new 3D design. Memory was designed for integration with VeSTIC (Vertical Slit Transistor-based Integrated Circuits) technology, to increase the circuit density to effectively use available space. This memory operates in relative environment, with control voltage not exceeding 9 V. Test simulations of memory cell indicate, that it has the capability to hold even more than 2 bits of information data. This design opens new possibilities for integration of advanced integrated circuits with dedicated non-volatile memory in a single chip with maximum device density.