Implementation of Hardware Trace Buffer Module for RISC-V Processor Core

Debugging of modern embedded systems can be very challenging due to the close cooperation of many independent components they consist of. The necessity to maintain timing dependencies during the debugging process of one component requires using non-intrusive methods, such as instruction tracing. In this paper we present a Verilog RTL implementation of a trace buffer module for a single-issue RISC-V processor. Our trace buffer is capable of adapting signals available in processor core to make any single-issue RISC- V processor compatible with the encoder interface. The system produces and saves enough data to reproduce the program flow based on the collected data, the program binary and firmware source code. The generated data packets are stored inside the internal FIFO buffer that can be reached through the configuration and status register interface, as well as passed to the transport layer. The implementation follows the Efficient Trace for RISC- V specification. The implemented module has been functionally verified including RISC- V reference test vectors. The design was synthesized with Yosys synthesis tool and FreePDK 45nm standard cell library.