Employing Parallelization Technique to Reduce Area and Power in a Booth Encoded Algorithm-Based Multiplier

This paper discusses the improvement of the multiplication operation speed in multipliers based on Booth's algorithm. The main goal of Booth's algorithm is to reduce the number of partial products by half, as a result of which, the multiplication operation will be completed sooner. The method proposed in this paper to solve this problem is designing a parallel multiplier using only one Booth Encoder circuit and one adder circuit. With the help of a series of circuits and control signals, these two circuits work in parallel and simultaneously so that the speed of the multiplication operation is not affected much. The production of partial products and their accumulation is being done in parallel. At the same time, the amount of hardware that is directly related to the power consumption is significantly reduced. The presented design is implemented in CMOS technology and 0.18um process. The proposed multiplier produces the correct output after 78nsec, and its operating speed is 12.8 MHz. The average power consumption of this multiplier is approximately 1.09 mW, and the number of transistors required for its construction is 2927.