10-Bit ADC SAR with Passive Charge Redistribution in 40nm CMOS Technology

This paper presents the design and simulation results of a 10-bit successive approximation analog-to-digital converter with passive charge redistribution. The design was realized in CMOS 40nm process and is foreseen for multichannel measurement integrated circuits. The main requirement of the presented design was ultra low power consumption and small area occupancy, which would allow for placing independent converter in each input channel. The paper describes in-detail the converter operation principle and design solutions that aimed at on-chip implementation.