Efficient Data Packet Sorting Method Based on Field-Programmable Gate Arrays On-Chip Random Access Memory

Research on efficient sorting algorithms is always an important research direction. The time complexity of traditional sorting algorithms is
$\mathrm{O}(\mathrm{n}^{2})$
or
$\mathrm{O}(\mathrm{n}\times\log_{2}\mathrm{n})$
, which still needs for further improvement. Due to its support for parallel computing and good real-time performance, FPGA has become one of the choices for algorithm acceleration. In this paper, a more efficient data packet sorting method based on FPGA's on-chip random access memory is proposed. This method establishes a mapping relationship between the feature field of data packets and the addresses of FPGA on-chip random access memory, and then writes the data packets into the RAM according to the mapping relationship. Due to the ordered nature of RAM addresses, the data packets written into the RAM naturally form an ordered queue when read out in address order. During the process of reading the RAM, an index registers are used to mark the status of each address of the random-access memory, thereby skipping empty addresses and only reading the addresses that store valid data packets. This method fully utilizes the hardware features of FPGA, not only transforming the complex sorting process into simple RAM write operations, but also requiring only 2 clock cycles to sort each signal, thus reducing the time complexity to O(n).