Designing Enhanced Monte Carlo Power Depletion Simulation in PSPICE

PSPICE is a member of the SPICE family and is widely used for simulating different types of circuits in various applications. To accurately measure average power consumption, Monte Carlo simulation is often used as an indirect method. This involves integrating an auxiliary power testing circuit into the PSPICE simulation. However, voltage drops may occur unexpectedly at stable states and boundaries during simulations of CMOS and pass transistor logic (PTL) circuits, even though power consumption should always be positive. This discrepancy occurs because the auxiliary power testing circuit is only connected to the power source V
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, ignoring the contribution of input signals to the circuit’s overall electric energy. This oversight becomes significant, especially in cases where input signals are complex. As a solution, we propose a modified Monte Carlo model where an auxiliary power testing circuit is incorporated into each individual input source to account for power consumption accurately. After comparing and analyzing the simulation results between the conventional and modified Monte Carlo methods, we observed the elimination of unexpected voltage drops and a significant improvement in result accuracy with the modified design.