GaN FET Versus MOSFET Dead Time Losses Comparison in Half-Bridge Configuration

The paper aims to study the dead time range in which the GaN FET and the MOSFET perform lower commutation energy losses in inverter topology for motor drive applications. To pursue the paper investigation, two experimental boards with similar layouts differing only in mounting GaN FET and equivalent silicon MOSFET in half-bridge configuration have been used to evaluate the dead time losses at varying of the current level typical of inverter applications. Furthermore, switching node voltage transient measurements demonstrate a dependence on the phase current amplitude and direction, the chosen dead time, and the transistor technology. The paper develops and validates a model to replicate the half-bridge experimental setup to understand the commutation transient and reverse conduction behaviour during the dead time. From the experimental test and simulation runs, the paper contributes to establishing the theoretical foundation and guidelines for selecting an appropriate dead time duration based on the current load to minimize energy losses for GaN FET devices compared with MOSFETs.