FPGA-Based Unit for Selective Harmonic Elimination in Voltage-Source Inverters

Many electric drives, such as railway traction machines, are designed to be operated in an overmodulation region and in six-step mode, where the motor voltage waveform is distorted by low-order harmonics. The Selective Harmonic Elimination (SHE) method is an effective solution to reduce these unwanted harmonics. The SHE algorithm requires solving complex transcendental equations, traditionally tackled using algebraic or genetic algorithms. Historically, these equations were pre-solved, and the resulting switching angles were incorporated into microprocessors through Look-Up Tables (LUTs) and were selected based on the reference voltage. However, with the decreasing cost of electronic components, Field-Programmable Gate Arrays (FPGAs) have become a viable option for real-time computation of these equations. This paper validates the effectiveness of the SHE method in the common three-phase two-level Voltage Source Inverter (VSI) by implementing an off-line FPGA-in-the-Loop setup, integrated with MATLAB
^®
and Simulink
^®
environments, where the VSI and load are modeled. The Verilog FPGA computational modules designed in this paper were rigorously simulated and, upon achieving successful results in behavioral simulations, they were synthesized and deployed on a development board featuring a System on Chip (SoC) with an integrated FPGA.