Comprehensive Experiments and Modeling Applicable for Ferroelectric Transistors With an MFMIS Structure and a Wide Range of Area Ratios: Unveiling the Operation Mechanisms

In this study, we performed comprehensive experiments and modeling to gain a deep understanding of the impact of various key factors on the characteristics of ferroelectric field-effect transistors (FE-FETs) having a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure. We investigated the effects of ferroelectric (FE) polarization switching, charge trapping (CT) in the floating gate (FG) from both the control gate (CG) and channel directions, as well as soft breakdown (SBD) of the FE layer. These investigations were carried out across a wide range of area ratio (AR) spanning from 1:1 to 1:1000. Through a combination of extensive experiments and rigorous experiment-simulation interactions, we arrived at several key conclusions: 1) in devices with large ARs, device behavior is primarily influenced by CT from the channel direction, resulting in a negative memory window (MW) with a clockwise (CW) direction; 2) the positive MW of the FE-FETs can overcome the limitation of
$2{V}_{\text {C}}$
(
${V}_{\text {C}}$
is the coercive voltage of the FE layer), thanks to FE switching and the combined effect of CT in FG from CG. This is further supported by experiments involving the replacement of the FE layer with a standard HfO2 layer; 3) as AR decreases, the impact of FE polarization diminishes, and CT in FG from CG gradually becomes the dominant factor affecting device characteristics; and 4) SBD becomes prominent as AR decreases to a certain threshold, leading to a very large MW and a step subthreshold swing (SS). Inspired by these findings, we developed a comprehensive and accurate model that incorporates FE, CT, and SBD effects. This model demonstrates excellent agreement with experimental data. Based on our experiments and simulations, we proposed and characterized five operation modes of the MFMIS structure, offering valuable insights for further device optimization and practical applications.