High-Throughput and Hardware-Efficient ASIC-Chip Fabrication of Reconfigurable LDPC/Polar Decoder for mMTC and URLLC 5G-NR Applications

This manuscript proposes hardware-efficient and high-throughput reconfigurable architecture of the channel decoder for unified decoding of LDPC or polar code. It has been designed based on the new dataflow technique for reconfigurable decoding that incurs lesser hardware resources in the decoder design. In addition, this work presents memory-organized architecture that exploits the shared-memory hardware and also excludes various conventional sub modules. Furthermore, this reconfigurable LDPC/polar decoder has been ASIC fabricated in UMC 110 nm-CMOS technology node, occupying an area of 1.96 mm2. It supports multiple code-rates and code-lengths that are compliant to mMTC and URLLC applications of 5G-NR wireless communication standard. At the supply voltage of 1.2 V, the proposed decoder-chip operates at the measured clock frequency of 72.7 MHz and delivers a data throughput of 3.35 Gbps that is
$4{\times }$
higher than the state-of-the-art implementation. It also consumes 15.8% lesser area and achieves
$2.5{\times }$
better hardware-efficiency in comparison to the contemporary works.