Parameters optimization to minimize the power dissipation of FiNFET 7 nm

FinFET device represents an alternative solution to overcome the Short Channel Effect (SCE). In this paper, a layout based FinFET design approach has been presented at 7 nm node technology using Spice model. The different electrical performance and characteristics of both N and P FinFET 7 nm have been studied to realize the CMOS circuits such as CMOS NOT gate, CMOS NOR and CMOS NAND. The original contribution of this paper is to present an impact parameters of load capacitance ($\mathrm{C}_{\mathrm{L}}$), supply voltage ($\mathrm{V}_{\mathrm{DD}}$) and gate width ($\mathrm{W}_{\text {gate) }}$ on the total power to have optimal CMOS circuit using Spice latest model. The simulation results show that the minimum total power can reach with $\mathrm W_{\text {gate}}=16 \mathrm{~nm}$ and $\mathrm {V_{DD}}=0.65 \mathrm{~V}$ for CMOS NOR gate. The optimal load capacitance is 0.5 fF for CMOS NOT Gate.