Delay Aware Reduced SPEF STA

Static timing analysis is one of the important aspect of IC Design signoff. The accuracy of the parasitic RC extraction, the completeness of the modelling library, the qualification of the EDA tools, and the completeness of the timing constraints are all factors that determine the quality of the static timing analysis and the timing signoff. The quantity of nets and instance counts grows in tandem with the growing complexity of designs made possible by technological advancements. Hence, the netlist file size, parasitic file size and library file size with multi corners required increases accordingly for the timing signoff. This imposes challenges in the disc space, memory and server requirements for the fullchip timing signoff. In this paper, a delay aware reduced SPEF methodology for accuracy static timing signoff is proposed, to reduce the disc space and potentially runtime in fullchip timing signoff. The results shows 75% file size saving, slightly improved runtime in block level execution and comparable accuracy compared to full SPEF STA. Hopefully, the design community will benefit from the sharing.