Gate Drive Method for Reducing Threshold Voltage Drift of Silicon Carbide MOSFET

The issue of dynamic threshold voltage drift in silicon carbide (SiC) metal-oxide–semiconductor field-effect transistors (MOSFETs) exacerbates their on-state resistance and conduction losses, thereby constraining their broader application. The dynamic threshold voltage drift in SiC MOSFETs occurs only under bipolar gate voltage stress, while it is not significant under unipolar gate voltage stress. Therefore, there exists the possibility of using a multilevel gate drive that divides the bipolar switching process of SiC MOSFETs into two stages of unipolar switching processes to suppress dynamic threshold voltage drift. Consequently, in this article, the effectiveness of multilevel gate drive is analyzed based on the previously reported local electric field enhancement model. In addition, a set of arbitrary level generator and a single-phase inverter experimental platform were designed for experimental validation. The findings reveal an inhibitory effect of multilevel gate drive on the dynamic threshold voltage drift of SiC MOSFETs. The research presented in this article holds reference significance for reducing the threshold voltage drift in SiC MOSFETs and improving device reliability and lifespan.