Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric-Stacked Negative Capacitance Multigate FETs at Sub-3 nm Technology for Digital/ Analog/RF Applications

In this study, for the first time we benchmark the dc/analog/RF performance of dielectric/ferroelectric (FE)-stacked negative capacitance (NC)-based multigate devices, including FinFETs, nanowire (NW)FETs, and nanosheet (NS)FETs, at the sub-3 nm technology node’s ultimate scaling limit involving a fully calibrated 3-D TCAD simulation. Exploring a design space to eliminate negative differential resistance (NDR) and optimize performance, we varied parameters such as gate length ( ${L}_{\text {g}}\text {)}$ , fin thickness ( ${T}_{\text {fin}}\text {)}$ , fin height ( ${H}_{\text {fin}}\text {)}$ , NW diameter ( ${D}_{\text {NW}}\text {)}$ , NS width ( ${W}_{\text {NS}}\text {)}$ , and NS thickness ( ${T}_{\text {NS}}\text {)}$ . The analysis shows that the NC-NSFET outperforms NC-FinFET, exhibiting an improved SS, enhanced intrinsic gain ( ${A}_{\text {V}}\text {)}$ of ~15% and a $3\times $ improvement in cut-off frequency ( ${f}_{\text {T}}\text {)}$ . Notably, NDR effects were observed for ${L}_{\text {g}} \lt 15$ nm in all devices and for NC-FinFET, downsizing ${T}_{\text {fin}}$ and ${H}_{\text {fin}} \lt 5$ nm and <30 nm, respectively; for NC-NSFET, scaling ${T}_{\text {NS}}$ and ${W}_{\text {NS}} \lt 5$ nm and <18 nm, respectively. Additionally, NC-NSFET demonstrated a ~50% reduction in negative drain-induced barrier lowering (DIBL) when compared to NC-FinFET. At lower ${L}_{\text {g}}$ , the ${f}_{\text {T}}$ is noticed to be improved by an amount of ~6.6%, ~17.4%, and ~23.7% for NC-FinFET, NC-NWFET, and NC-NSFET, respectively, with better performance noticed for NC-NSFET. By downscaling the ${T}_{\text {fin}}$ to $\sim 3.6\times $ , the ${A}_{\text {V}}$ and ${f}_{\text {T}}$ is found to be improved by ~42.6% and ~21.5%, respectively. However, scaling the ${H}_{\text {fin}}$ resulted in better improvement in fT by ~48.47%. By downscaling the ${T}_{\text {NS}}$ , the ${A}_{\text {V}}$ and ${f}_{\text {T}}$ are improved by ~28.13% and ~46.19% while scaling the ${W}_{\text {NS}}$ , the ${f}_{\text {T}}$ is improved by ~45.96%. Overall, this research establishes the NC-NSFET as a frontrunner proving itself as the optimal choice for analog/RF applications in the realm of nanoscale semiconductor technology.