MOSFET Probabilistic-Bit Behavior

Probabilistic computing is a physics-based beyond-von-Neumann framework proposed to meet the high energy-efficiency and performance demands of modern AI and combinatorial optimization problems [1] . A probabilistic computing platform is a control loop made up of probabilistic-bits (p-bits), which are essentially tunable random-number-generators (RNGs) [2] , and classical circuitry that updates the p-bit inputs ( Fig. 1a ). When a p-bit’s input is high, it is usually “1”, and when a p-bit’s input is low, it is usually “0” ( Fig. 1b ); in-between is a stochastic region wherein the probability that the p-bit is “1” follows a sigmoid function of the input. A p-bit typically is constructed with a tunable probabilistic element and a CMOS circuit (comparator or inverter) to amplify the signal. All p-bit demonstrations thus far rely on emerging devices (or CMOS emulations) that display probabilistic behavior [1] . Recently, a transistor with an unstable ferroelectric gate stack layer (FeFET) was proposed to implement a p-bit [3] . Since current flow in a conventional MOSFET involves the transport of an ensemble of particles, it can exhibit probabilistic behavior and therefore has been investigated for RNG based on the Random Telegraph Noise (RTN) phenomenon [4] due to trapping and detrapping of charge carriers from the channel of a MOSFET causing fluctuations in carrier mobility and density. By leveraging the drain voltage or gate voltage dependence of RTN, a p-bit could be formed as illustrated in Fig. 1c or in Fig. 1d , respectively. In this work, we experimentally investigate the bias voltage dependence of RTN.