Analyzing the Dynamics of Store Mechanism and Data Retention through Transient Simulations in Si/Ge TRAM for Cryogenic Memory Applications

Gated thyristor-based single transistor (1-T) dynamic RAM (TRAM) is a promising candidate as cache memory for high-performance computing (HPC) systems at cryogenic temperatures [1] . Its large ON/OFF ratio offers fast read/write speed; low operating voltage, long retention, and non-destructive read operation lead to very low power consumption; and the FinFET compatible 1-T cell structure enables high density. The memory storage mechanism is of fundamental importance and crucial for device design considerations. In many earlier works [2 , 3] , the storage mechanism has been perceived as accumulation (‘1’) or depletion (‘0’) of holes in the p-base regions, whereas a few later studies [4] have defined the states as absence (‘1’) or presence (‘0’) of deep depletion regions in the device. Through transient simulations over data retention time, this article elucidates the store mechanism in terms of modulation of hole density and electrostatic potential. The article also discusses the time dependence of the primary data loss mechanisms during retention in Si or Ge-based TRAM, which explains the reason for the long data retention time (> 10 5 s) at cryogenic temperatures [1 , 5] more clearly.