CMOS+X Technologies for Neuro-Vector-Symbolic Computing

Neuro-vector-symbolic (NVS) computing aims to combine neural models with vector-symbolic architectures (VSA), also known as hyperdimensional computing (HDC) built upon vector arithmetics in the high-dimensional space [1] . NVS computing merges human-like symbolic learning and reasoning with hierarchical, context-based neural representations, marking a key development in the third wave of artificial intelligence represented by Neuro-Symbolic AI [2] . With heterogeneous model architectures embedding diverse backbones and multiple data representations, NVS computing promise the next level of learning capability, robustness, and explainability. Deep neural networks (DNNs) [4] and spiking neural networks (SNNs) [5] in general, with specialized convolutional neural networks (CNNs) [3] and transformers [6] , may form multi-modality neural backbones. VSA components [7] [8] [9] enhance cognitive reasoning, continuous learning, and domain adaptation. With NVS models handling data-intensive workloads, tailored hardware platforms are needed for sustained efficiency bridging the edge-cloud continuum. Targeting NVS-AI hardware, it is essential to have energy-efficient compute kernels optimized in a fine-grained fashion for various NVS components, as well as flexible architecture integration. These two critical needs can be met if we jointly exploit the 3D integration platforms and emerging device technologies with silicon CMOS foundation (“CMOS+X”), due to the vast design space exposed from material/device level to architecture level. We provide an overview of emerging device technologies which may enable system integration of hybrid neural and vector-symbolic models through NVS co-designs.