Three-Input Combinational Logic Gates based on Reconfigurable Si Field-Effect Transistors

Reconfigurable field-effect transistors (RFETs) are an emerging device concept with increased functionality and configuration flexibility, overcoming limitations of rigid conventional CMOS technologies relying on static operation schemes. Making use of an additional gate-electrode, the so called polarity gate (PG), the device can be dynamically switched between n- and p-mode characteristic at runtime, enabling new device concepts for adaptive computing and logic gates with reduced transistor count and latencies. [1 , 2] Especially minority (MIN), majority (MAJ) or XOR based logic benefit from the symmetrical fine-grain reconfigurability, as their implementation in conventional CMOS technology is rather complex. Moreover, the reconfigurability at the device level has been identified as primitives for hardware security circuits. In this work, we demonstrate the physical implementation of these three input combinational logic gates, realized with highly on-state symmetric Si RFETs.