Optimization of Backside of Silicon-Compatible High Voltage Superlattice Capacitor for 12V-to-6V On-Chip Voltage Conversion

Backside power delivery with buried power rail (BPR) is one of the enabling technologies for 2 nm node and beyond [1] . Moving one step further, we believe that integrating active components in the backside of silicon, e.g., integrated voltage regulator (IVR), could provide further improvement in power conversion efficiency by minimizing the IR drop at the package/interposer level [2] . To minimize the power delivery loss, it is advantageous to place the IVR close to the voltage source (e.g., 12 V from the package/interposer) and perform voltage down conversion near the point of loads. However, most of the reported monolithic IVRs so far are placed at the frontside of silicon. One of the core elements in IVR is the flying capacitor. Unfortunately, today’s on-chip back-end-of-line (BEOL) compatible metal-insulator-metal (MIM) capacitor is mostly designed for handling voltage of <3.3 V. In this regard, it is timely to explore new capacitor technology featuring (1) backside of Si integration, (2) high breakdown voltage (> 6 V) (3) sufficient reliability (>10 yrs @ 85 °C) and (4) high 2D capacitance density (> 28 fF/μm 2 ) to pave the pathway for “active” backside power delivery to deliver >1 W/mm 2 power density. To the best of our knowledge, we report the first experimental demonstration of a Hf 0.25 Zr 0.75 O 2 /Al 2 O 3 laminate-based superlattice capacitor serving as the flying capacitor in a 12V-to-6V IVR. The stack is optimized to achieve the core requirements (1)–(3), and extensive reliability characterizations are performed for the lifetime projection based on the conduction mechanism.