90 Degree Video Rotation Design Based on FPGA

In order to reduce the resource overhead of video rotation processing without compromising the video display quality, a custom method based on the FPGA platform was adopted to process real-time video streams with 90-degree rotations. The read and write logic design from the FPGA end to the DDR3 SDRAM end was completed, utilizing a three-level cache for ping-pong operation and a multi-channel read/write arbitration module for channel management to achieve real-time image caching. Experimental results indicate that the video rotation scheme designed in this project enables real-time rotation by 90 degrees for videos of arbitrary resolutions without additional DSP and interpolation algorithm logic. It consumes less FPGA logic resources, occupying only 418 Slice LUTs, 494 Slice Registers and 1 DSP resources. The image is clear and smooth, without flickers, jitter and misalignment. It is especially suitable for applications where the digital logic area is tight or the cost is high.