An FPGA-based QC-LDPC encoder design

Low-density parity-check (LDPC) codes have been widely used to deal with noise interference and improve the reliability of the system due to their excellent error correction performance. At the same time, with the increase of storage density in digital storage devices, LDPC codes are also applied to the error checking and correcting (ECC) module to solve the situation of random flipping of stored data bits. In this paper, the progressive edge growing (PEG) algorithm is used to construct a high-rate Quasi Cyclic-LDPC (QC-LDPC) code suitable for the ECC module of the storage device, and the generator matrix is analyzed, and finally a high-efficiency encoder is designed based on the FPGA to quickly generate the parity-check bits in the storage device. The encoder in this study can achieve a throughput of 106.4Mbps at a 50MHz clock.