Occurrence of Voids in Soldered Joints for Electrical Engineering

The research focuses on the occurrence of voids in soldered joints in the field of electrical engineering. The main goal was to analyze the occurrence of voids in soldered joints and to propose effective strategies to minimize this defect. BGA chips mounted on 10-layer PCBs were chosen as test samples. The current work focuses on defining production conditions and analyzing X-ray images. The analysis results implies that the parameters were chosen correctly and the acceptability criteria according to the ECSS-Q-ST-70-61C standard (defining soldering qualification for the space industry) were met with a margin, allowing for further types of tests such as vibration test and temperature cycling.