TCAD model of GAA Nanowire Transistor with silicon oxide/nitride/oxide dielectric

For the needs of nanoelectronics, a JL FET model has been developed. Gate-All-Around Transistor Computer-Aided Design (TCAD) technology is implemented in COMSOL. The structure is composed of a 2 µm silicon nanowire, with a nanowire cross-section of 10 × 10 nm, surrounded by the sub-gate dielectric of a silicon oxide/nitride/oxide (O/N/O) layer and the channel length 50 nm formed by Gate-All- Around poly-Si with work function 4.2 eV. The simulated I-V characteristics are compared with experimental data and the accuracy of the model is estimated to be 9.5 %. It is like technological tolerance. Then, the I-V characteristics of the same structure, but with a silicon oxide sub-gate dielectric, are simulated. A comparison and analysis of the characteristics and I
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ratio of the two structures with different dielectrics was made and it was found that the structure with a higher permittivity is more suitable for nanoelectronic applications, including memories.