A Linearity Improved Equalizers for Short-Channel Communication Links

The paper introduces a novel Continuous-Time Linear Equalizer (CTLE) circuit aimed at improving linearity by replacing conventional current sources with high-linear poly resistors. A key innovation lies in the adoption of a Voltage-to-Current (V2I) converter instead of the conventional current source in the CTLE bias circuitry. This strategic change directly targets the main sources of linearity limitations, setting this approach apart and introducing a more effective means of managing bias currents in the CTLE. The anticipated benefits of this innovative modification include a significant enhancement in circuit linearity performance and a consequent reduction in Total Harmonic Distortion (THD). The proposed CTLE has been designed using a standard 65nm CMOS technology, with a 1V power supply and an active area of 0.023mm
²
. The post-layout simulation results confirm that the CTLE operates correctly. It demonstrates superior performance for a 12-inch channel at a data rate of 12.5 Gb/s, with an eye width of 71.24 ps, an eye height of 98.82mV, and a jitter of 8.63 ps. The proposed CTLE consumes 3.29mW, exhibiting a FoM of 0.26 p
^J/b
. These advancements in the CTLE module represent significant progress in optical circuit innovation, signalling a meaningful stride toward achieving enhanced performance and reliability in modern circuit designs