Asynchronous Coarse-Grained Reconfigurable Computing Architecture for Matrix Inversion

Matrix inversion is a fundamental operator in MIMO (multiple-input multiple-output) technology, which is a key technology in wireless communication. MIMO technology is characterized by a strong correlation between its underlying operations and matrix inversion. Traditional Von Leuwen archi-tecture processors are limited by the performance bottleneck of sequential execution, which hinders the performance of matrix inversion and limits the development of MIMO technology. The paper proposes a self-timed dynamically reconfigurable architecture to address the performance bottleneck caused by sequential execution in matrix arithmetic. This bottleneck has limited the development of MIMO technology. The architecture consists of several coarse-grained operators interconnected by an on-chip network to form an array for massively parallel computation. The experiments were conducted using an FPGA platform. The results demonstrate that the proposed architecture in this paper has excellent solving performance while significantly reducing the power consumption of the entire system. Specifically, when solving the inverse matrix of a fourth-order matrix, the dynamic power consumption is only 1.976W.