IR Drop Analysis for Power Integrity in 3D ICs

Die stacking provides an upper hand in terms of efficiency, power reduction or power performance efficiency, reduction in area overhead, and overall functional density. However, power integrity remains a prevalent issue. The tradeoff lies between the reduction in footprint, improved form factor, and power integrity. Through silicon vias (TSVs) plays an important role in vertical stacking which can contribute significantly to the losses between the tiers due to its impedance parasitics. This paper analyzes the power integrity issue regarding IR drop in each tier of a three-dimensional (3D) integrated circuit (IC). The dynamic and static IR drops in 3D ICs have been analyzed and a solution for reducing the IR losses has also been proposed.