A Simplified Volterra Approach to Non-Linear ADC Post Correction

This paper proposes a foreground digital calibration approach for the correction of nonlinearity in an under-sampled high-speed Time-Interleaved Analogue to Digital Converter (TI-ADC) using a modified Volterra series model. The reduction in the model size is done via the restriction in the allowable deviation between samples in product terms. The proposed correction algorithm was firstly verified in simulation and validated using real data collected from a a Xilinx ADC with an aggregate sampling rate of 4.096 Gsps operating in the 2nd Nyquist zone. The results show a 20–47% complexity reduction compared to conventional Volterra Models with comparable performances (as measured in term of SFDR performance).