High speed low leakage and power efficient Domino Logic circuit for wide fan in gates

Domino logic are crucial in VLSI circuit design due to their superior performance, smaller footprint, and low power consumption. Despite their widespread use, issues such as propagation delay and leakage power remain a significant drawbacks. However, these challenges have been and will continue to be addressed. In today's rapidly advancing technological landscape, there is a growing demand for faster and more energy-efficient circuits. This paper present a high-speed and power-efficient domino logic circuit by enhancing charge sharing in a charge pump based design. By leveraging stacking effects and isolating transistors, delays and leakage currents are minimized during the pre-charging and evaluating phases. As a result, the domino circuit proposed demonstrates enhanced speed and power efficiency in contrast to current domino circuits. The circuit's operational efficiency has been evaluated through simulations using Tanner Tools and its 180 nm technology library file.