Automatic Generation of System Verilog Assertions for Verification of Safety Mechanisms

The prevalence of safety-critical applications has increased, resulting in a heightened demand for designs that prioritize functional safety. These designs are characterized by the inclusion of injected safety mechanisms. The goal of this paper is to propose an automatic verification flow to validate the functionality of added safety mechanisms. The flow accommodates safety mechanisms such as parity checking, triplication, duplication, and error correction code. It detects the presence of safety mechanisms in the design and automatically generates appropriate assertions for their validation.