A Maximum-Likelihood-Estimation-Based Digital Background Calibration Technique for Interstage Gain Error in Pipelined ADCs

This paper presents a maximum-likelihood-estimation-based digital background calibration technique for interstage gain error (IGE) and capacitor mismatches in high speed pipelined analog-to-digital converters (ADCs). Compared with the other calibration methods, this all-digital calibration method eliminates the effect of white noise. Besides, there is no requirement for the capacitor mismatches of PN generation. It can also calibrate the capacitor mismatches of DAC in pipelined structure. Furthermore, this technique only needs one set of data to derive the error parameters instead of multiple iterations, which makes it converge faster. The scheme is validated in a 1-GSps 14-bit pipelined ADC in a 28 nm CMOS technology, similar to [1]. Behavioral simulations have demonstrated that the proposed calibration method improves signal-to-noise-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 39.56 dB/ 52.27 dB to 55.28 dB/ 86.16 dB, respectively.