Implanting Machine Learning Accelerator with Multi-Streaming Single Instruction Multiple Data Mechanism to RISC-V Processor

We proposed the architecture to accelerate machine learning computation with flexible and diversified features of the convolution-based models. The multi-streaming Single Instruction Multiple Data (SIMD) mechanism was built in the proposed accelerator architecture using the RISC-V processor to enhance the smooth instruction flow methods and the high bandwidth data access mechanisms. By analyzing the instruction flow and the data structure, which are needed for machine learning computing in parallelism, we added 87 new instructions for the proposed processor to make the programs of the optimal machine learning algorithms in the SIMD methods. Especially, for balancing the data access latency and the procedure computing time, we applied the locality addressing mode in the buffer space to suit the tiling computing model in famous to solve the machine learning algorithms. After analyzing the five classic convolution neural network models, the average execution speed increased 3.4 times of the ARM Cortex-M55 processor. It is equivalent to the execution speed of the personal computer when the proposed processor operates at 800 MHz frequency.