Chip Implementation and Assessment of Mixed-Mode in-Memory Computing

With the rapid advancement of technology, the application of artificial intelligence has also expanded quickly. The main driving force is the advancements in hardware technology and the optimization of algorithms. On the other hand, with the rise of the Internet of Things (IoT) and wearable devices, the majority of computation time is spent on data transmission, which has brought the concept of Computing In-Memory (CIM) into focus. However, CIM introduces many errors. Therefore, we formed an 1024 ✗ 256 CIM array chip fabricated by CMOS 0.25 µm foundry process in this work, using Non-Overlapped Implantation (NOI) MOSFETs as mixed-mode CIM units. In this study, a deep learning network architecture of a six-layer multilayer perceptron (MLP) was used, and 50,000 training samples from the Cifar-10 color image dataset were included as the training data for the model network. In the test set, 1000 continuous samples were selected to verify the model's reliability. The total number of parameters in the model was compressed to 457K, yet the model's recognition rate remains at 90.2%. Transfer learning was conducted through a microcontroller with about 43% of parameters transferred to Non-Overlapped Implantation for CIM. When NOI replaced the first layer of the MLP, it declined the recognition rate to 82.7%. This degradation in recognition rate occurred due to the output current inaccuracy produced by NOI devices under different voltages, the non-linearity issues of the current-voltage conversion circuits, and semiconductor process error. Compared to the use of pure M4, the hardware architecture improved computational time by 15.03% and weight memory storage by 42.51%, demonstrating the potential for enhanced computational efficiency and reduced energy consumption in CIM.