A Low-Area and Low-Power Architecture for Soft-Assisted Product Decoder

Product code has been proven as an efficient choice for achieving high net coding gain (NCG) at extremely low bit error rates (BER) in fiber communication systems. Compared to the hard-decision product decoders, it has been demonstrated that decoders based on soft-assisted decoding algorithms can achieve excellent decoding performance with only a slight increase in area. However, existing decoders tend to have high power dissipation and large component decoder area due to the fully-parallel architecture. Therefore, further efforts are needed to achieve efficient hardware implementation. In this paper, a low-area and low-power product decoder based on Improved Soft-Assisted Iterative Bounded Distance Decoding algorithm (ISA-iBDD) algorithm is presented. The ASIC synthesis results show that the proposed design leads to an 8.5× improvement in area efficiency (AE) and a reduction of 62% in energy dissipation compared with the state-of-the-art design.