Large-Scale Parallel Embedded Computing With Improved-MPI in Off-Chip Distributed Clusters

Distributed architecture is expected to be an effective solution for large-scale edge computing tasks in terminal devices. However, it remains a great challenge to resolve the conflict between parallel efficiency and constrained physical resources in a specific embedded structure. This article proposes a universal scalable off-chip parallel computing architecture to maximize the computing efficiency for distributed embedded computing clusters. This architecture is based on an improved Message Passing Interface (Improved-MPI). To address the limited communication speed in embedded environments, a multilevel communication mechanism is employed to alleviate the communication pressure on nodes. By flexibly allocating computing tasks, efficient utilization of every embedded cluster node is ensured, while also solving the problem of single point of failure. In addition, to overcome the challenge of limited RAM in embedded devices, the architecture utilizes the interleaved memory initialization mechanism to run larger computing tasks. Based on this architecture, a specific embedded cluster platform is constructed using the RK3399 board. Various large-scale tasks are deployed on this platform to validate the performance of the architecture. First, a large-scale randomly connected neural network is executed, which serves to verify the architecture's outstanding computational performance and communication capability. Secondly, a functional model of Small-World Spiking Neural Network is constructed, achieving real-time and efficient digital speech recognition. Finally, the implementation of Large Language Models demonstrates that the embedded clusters can achieve performance comparable to modern computers.