RISC-V Simulator Library for Real-time Applications: Development and Verification

This paper extends RISC-V processor functional simulators with timing libraries for fast and accurate results. To this end, we develop timing libraries for the floating point unit (FPU) and the AHB Interconnect, which are frequently used and affect the performance of real-time embedded signal processing applications. Our FPU timing library is verified to be nearly 100% accurate through experimental comparisons with a low-level RTL simulator. Our interconnect timing library yields the expected cache and memory communication scenario results.