Secure Boot Design for a RISC-V Based SoC and Implementation on an FPGA

The FPGA-based RISC-V system is a system that utilizes the open-source RISC-V processor architecture and is implemented on FPGA (Field Programmable Gate Arrays). This system provides flexibility and customization options, allowing for tailored solutions for different application domains. Securing the boot process of systems composed of widely used open-source and customizable structures is a critical requirement to maintain data integrity and ensure system security. This study presents a model for implementing secure boot processes using a hardware-based TPM 2.0 module on the FPGA-based RISC-V system, encompassing both software (operating system components) and hardware components. The components required for the RISC-V SoC (System on Chip) and the TPM 2.0 module to be used in secure boot have been implemented on the FPGA development board and functionally verified.