Optimization of the SPHINCS+ PQC Algorithm with Custom Instructions and LLVM Integration on a RISC-V Processor

With the emergence of quantum computers, traditional open key cryptographic schemes have faced an existential threat that necessitates the development of quantum resistant algorithms. Post Quantum Cryptography (PQC) has emerged as a solution that opposes this new cryptoanalytic evolution with hash based signature schemes such as SPHINCS+, known as one of the leading candidates by NIST. However, SPHINCS+ requires hardware acceleration for practical use. This study offers a method to accelerate the SPHINCS+ algorithm running in the RISC-V processor on the FPGA using the LLVM integration for custom instruction extension. Custom instructions have been developed for the SHA-256 operations, a fundamental component of SPHINCS+, resulting in a 5.09 x acceleration of the algorithm.