A Low-Loss DC-to-300 GHz InP/Si Interconnection Based on Wafer Level Packaging Using Chip-first/Facedown Process

This paper presents a low-loss broadband interconnect technology based on wafer level packaging (WLP) using chip-first/facedown process with sub-terahertz (sub-THz) bandwidth for InP/Si heterogenous integration. This technology has the advantage to reduce the insertion loss at a chip interconnect for the following two reasons. First, the interconnect structure on the re-distribution layer (RDL) is designed as the coplanar waveguide (CPW) which has the same impedance as the on-chip CPWs. Second, the contact vias between the interconnect CPW and the on-chip CPWs are fabricated as small as possible (3-μm-height) to reduce reflection. We fabricated the InP/Si WLP including a 250-μm-length interconnect CPW. It achieves an insertion loss between InP/Si chips of less than 1.8 dB from DC to 240 GHz and 4 dB at 300 GHz by S-parameter measurements. To the authors' knowledge, this is the lowest insertion loss between InP/Si chips using WLP technology in the sub-THz band.