Automated mmWave Power Amplifier Design Flow and a 28-GHz Design Example in 45-nm CMOS SOI

This paper presents an automated design flow for synthesizing high-efficiency yet high-linearity mmWave power amplifiers (PAs). The proposed design flow involves optimizations of active devices and passive networks, which determine the optimum biasing and size of transistors and optimum geometric parameters of transformer-based matching networks, respectively. The automated design flow is adaptable across a wide range of power levels and operating frequencies. Utilizing this design flow, a 28-GHz PA prototype is synthesized in the GlobalFoundries 4S-nm CMOS SOI process. It achieves state-of-the-art efficiency and linearity performance, with 19.2-dBm
$\mathbf{P}_{\mathbf{SAT}}$
, 18.6-dBm
$\mathbf{OP}_{1\mathbf{dB}}$
, 41.6% PAE at
$\mathbf{OP}_{1\mathbf{dB}}$
in the continuous-wave (CW) measurement. It also realizes 13.8-dBm average output power
$(\mathbf{P}_{\mathbf{avg}})$
and 26.4 % average PAE
$(\mathbf{PAE}_{\mathbf{avg}})$
at -2S.3-dB EVM when amplifying a 400-Msym/s 64-QAM signal.