An 11.8mW 0.4-to-2.6GHz Blocker-Tolerant Receiver with LO Duty-Cycle Compensation and High-Q Selectivity Achieving +15.4/19.2dBm OB-IIP3 at 10/80MHz Offset

This paper presents a mixer-first blocker-tolerant receiver (RX) with LO duty-cycle compensation and high-Q selectivity. A novel technique is proposed to mitigate noise figure (NF) and out-of-band (OB) IIP3 performance degradation caused by reduced LO drive capability at high frequencies. LO duty-cycle compensation is designed with the bias-tunable mixer to improve NF and OB-IIP3 at the high operating frequency while avoiding the large power consumption of LO drivers. Moreover, the proposed RX topology achieves high-Q selectivity by combining an auxiliary N-path filter at RF and an analog finite-impulse-response (AFIR) filter at baseband (BB). The RX prototype, fabricated in a 55-nm CMOS process, achieves wideband tunable high-Q selectivity from 0.4 to 2.6GHz. The RX achieves +15.4/19.2dBm OB-IIP3 (at 10/80MHz offset) and 2.4 to 3.5dB NF, while consuming 5.4 to 11.8mW power consumption, of which the LO drivers only need 2.9mW/GHz. The active chip area is only 0.29 mm
²
.