An Efficient Ku-Band Two-Way Vertical-like Power-Combining Power Amplifier using Merged Inter-stage Transformers Achieving 23-23.4 dBm Psat and 45.2-46.6% Peak PAE in 65nm CMOS

We propose a novel power combining PA architecture that cleverly utilizes metal stacks to achieve both high output power and efficiency while maintaining a compact chip size in CMOS. Through the adoption of a two-way vertical-like power combining PA architecture featuring the merged inter-stage transformers, a PA with high efficiency and an area reduction of approximately 50% (about the size of a single PA) can be obtained. This architecture was implemented using a 65nm bulk CMOS process, and its feasibility was verified through precise measurements. The proposed PA demonstrates a gain of 26–27.3 dB, a P
sat
of 23–23.4 dBm, peak PAE of 45.2–46.6%, a P
1dB
of 22.7–22.9 dBm, and PAE
1dB
of 44.2–45.5% in the 13–15 GHz range. When tested using a 1-CC 64-QAM OFDM signal (PAPR 11.2 dB), the PA achieves an average output power of 16.9–17.7 dBm and an average PAE of 22–24.1% at 13–15 GHz (at −25 dB EVM
rms
).