Phased-Array-Compatible Area-Efficient D-Band Power Amplifiers in 45 RF SOI based on Cascade Stacking

This work presents a high-power, area-efficient power amplifier (PA) at 140GHz in 45 RF SOI CMOS. A cascade-stacked architecture that can sustain a larger output voltage swing is utilized to achieve a higher saturated output power (P
SAT
) in an area-efficient manner while allowing the PA to operate at the same standard supply domain. This architecture also allows the DC current of the stacked stages to be decoupled, enabling independent bias optimization for power efficiency. A two-way power-combined PA using this architecture is also implemented to boost the P
SAT
further. Measured results indicate that the unit PA operating at 1.2V achieves a gain of 32.7dB, P
SAT
of 16.4dBm, and peak power-added efficiency (PAE) of 12.7% with an active area of 0.098mm
²
, while the two-way power-combined PA achieves a gain of 32.1dB, P
SAT
of 19.2dBm, and peak PAE of 12.2% with an active area of 0.190mm
²
. The achieved P
SAT
and ITRS FoM represent the highest among state-of-the-art 140GHz CMOS PAs.